Low dropout (LDO) regulators are linear voltage regulators used to regulate an output voltage based on a supply voltage. For example, a memory chip may have a pump and a memory circuit including an LDO regulator. With an LDO regulator, the output voltage can be kept close to the supply voltage since the voltage drop across the regulator is small. However, since an LDO regulator needs to dissipate power across the regulator itself, power consumption may be a concern in designing or driving an LDO regulator.
Conventionally, the LDO regulator in the chip is always enabled when the chip is in a standby mode. FIG. 1 schematically shows waveforms, in a conventional technology, of a chip-select signal (CS#) applied to a memory circuit and an LDO enable signal (ENLDO) applied to an LDO regulator in the memory circuit. As shown in FIG. 1, when CS#goes high, ENLDO also goes high and thus the LDO is always enabled during the period in which the memory circuit is in the standby mode. Such a scheme may cause unnecessary power consumption by the LDO regulator.